C8PSK HART

Introduction

Since the introduction of HART in its original 1200 baud FSK version, a higher-speed option has been developed, using phase-shift keying (PSK) as modulation on the traditional 4-to-20mA analogue signal. Each transmitted symbol consists of one cycle of 3200 Hz, with one of 8 discrete phases (hence "C8PSK", coherent 8-way phase-shift keying). Thus, each transmitted symbol represents 3 bits, so the baud rate of 3200 gives a bit rate of 9600 bps. This allows about 10 transactions a second (or 15 in burst mode).

The bandwidth occupied by this signal is wider than that of FSK HART, at 800 to 5600 Hz, but the use of adaptive equalization to accommodate distortion above the 2500 Hz cutoff of a maximum-length HART network means that the wiring rules are unchanged.

The signal is specified as 250 microwatts (equivalent to 350mV rms into a 500-ohm test load), small enough to maintain compatibility with the underlying 4-to-20mA signal.

The C8PSK message structure

The central structure of a C8PSK HART message is the same as the FSK version, but the preamble is modified, and there are start and stop flags around the core message. The preamble is a series of 40 symbols with alternating values 6 and 2. The start flag consists of 4 symbols: 4, 1, 2, 1. The stop flag consists of 3 symbols: 0, 0, 0. The core HART message is passed through a scrambler function (according to the V27.ter specification) to protect against a sequence of repeating bits which could otherwise cause loss of phase synchronisation in the receiver.

In the basic HART message, bits 4 and 3 of the Start Delimiter byte are set to 0 and 1, to indicate that this is a synchronous physical layer (no inter-character gaps are permitted).

Compatibility

C8PSK HART is fully compatible with the 4-to-20mA analogue signal. In addition, any device supporting C8PSK must also support FSK HART, and interoperate seamlessly with such equipment. It is recommended that devices should fall back to FSK in the event of communication difficulties.

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